`timescale 1ns/1ps

module code (
    input Clk,
    input Reset,
    input Slt,
    input En,
    output reg [63: 0] Output0,
    output reg [63: 0] Output1);
    
reg [3: 0] Output1_Cache;

initial begin
    Output0 <= 0;
    Output1 <= 0;
    Output1_Cache <= 0;
end

always @(posedge Clk) begin
    if (Reset) begin
        Output0 <= 0;
        Output1 <= 0;
        Output1_Cache <= 0;
    end else if (En)begin
        if (Slt == 1'b1) begin
            Output1_Cache = Output1_Cache + 1;
            if (Output1_Cache == 3'b100) begin
                Output1 <= Output1 + 1;
                Output1_Cache <= 0;
            end
        end else begin
            Output0 <= Output0 + 1;
        end  
    end else begin
        
    end
end

endmodule